This invention relates to masks and, more particularly, to a method of modeling the main etching and over-etching time for a mask to simultaneously model mask critical dimension (CD) and phase shift.
Increasingly, chip makers are designing integrated circuits with critical dimension (CD) tolerances as tight as 32 nm. To meet such reduced feature sizes, phase shifting masks, instead of binary masks, are increasingly being used by chip makers. Conventional light sources and lenses, or binary masks cannot consistently transfer a chip design with such narrow device linewidths to a wafer. Phase shifting masks are effective in accommodating the printing of smaller device linewidths of wafers because such masks sharpen the light's effects on a resist during photoexposure.
Phase shifting masks conventionally include a mask layer, such as molybdenum silicide, deposited on a quartz substrate. The mask layer is then patterned, e.g., dry etched, to define a circuit pattern that is to be printed on a wafer. To pattern the mask layer to define the device features with the desired CD, a two step etching process is conventionally used. First, a main etching step is performed. The main etching step is responsible for much of the patterning of the mask layer as it is effective in removing unmasked portions of the mask layer. Second, an over-etching or side etching step is performed to further etch the mask layer. As a result of this two-step process, the phase shifting mask can be susceptible to significant phase variations. Therefore, there is a need for a modeling process to determine a main etching time and an over-etching time that will satisfy desired CD tolerances without imposing a significant variation in phase on the phase shifting mask.